commit 7163d0062bd589d5df18e225a4ca9ce7347d5adc
parent c92a6343f6a4c8ab748df09b09dce2abd373322f
Author: Gerd Beuster <gerd@frombelow.net>
Date: Sun, 7 Feb 2021 18:47:18 +0100
Bus logic toolchain switched to GALasm and minipro
Diffstat:
4 files changed, 82 insertions(+), 102 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -1,15 +1,8 @@
*~
-hw/bus_logic/BUS_LOGIC.abs
-hw/bus_logic/BUS_LOGIC.doc
-hw/bus_logic/BUS_LOGIC.jed
-hw/bus_logic/BUS_LOGIC.pdf
-hw/bus_logic/BUS_LOGIC.si
-hw/bus_logic/BUS_LOGIC.sim
-hw/bus_logic/BUS_LOGIC.lst
-hw/bus_logic/BUS_LOGIC.mx
-hw/bus_logic/BUS_LOGIC.pla
-hw/bus_logic/BUS_LOGIC.so
-hw/bus_logic/BUS_LOGIC.wo
+hw/bus_logic/bus_logic.chp
+hw/bus_logic/bus_logic.fus
+hw/bus_logic/bus_logic.jed
+hw/bus_logic/bus_logic.pin
sw/**/*.bin
sw/**/*.l
sw/**/*.lst
diff --git a/hw/bus_logic/BUS_LOGIC.PLD b/hw/bus_logic/BUS_LOGIC.PLD
@@ -1,91 +0,0 @@
-Name BUS_LOGIC;
-Partno ;
-Revision 01;
-Date 10/01/20;
-Designer gb;
-Company ;
-Location None;
-Assembly None;
-Device g16v8a;
-
-/* Bus logic for 8 bit computer based on 65C02
-
-Copyright 2021 Gerd Beuster (gerd@frombelow.net). This is free
-soft-/hardware under the GNU GPL v3 license or any later version. See
-COPYING in the root directory for details.
-*/
-
-pin 1 = rwb; /* cpu_RWB */
-pin 2 = i0; /* cpu_A15 */
-pin 3 = i1; /* cpu_A14 */
-pin 4 = i2; /* cpu_A13 */
-pin 5 = i3; /* cpu_A12 */
-pin 6 = i4; /* cpu_A11 */
-pin 7 = i5; /* cpu_A10 */
-pin 8 = reset_in; /* Reset logic output */
-pin 9 = phi; /* cpu_PHI2 */
-/* pin 11 = connected to cpu_A9, but not used at the moment */
-pin 12 = o0; /* eeprom_#ce */
-pin 13 = o1; /* ram_#oe */
-pin 14 = o2; /* I/O Devices */
-pin 15 = o3; /* ram_#ce */
-pin 16 = o4; /* I/O Devices */
-pin 17 = o5; /* I/O Devices */
-pin 18 = o6; /* ram_#we */
-pin 19 = o7; /* cpu_RESB */
-
-/* ROM (8k)
- Address range: 0xe000 - 0xffff
- Bit pattern: 0b111.............
- */
-
-o0 = (!i0 # !i1 # !i2);
-
-/* RAM (32k)
- Address range: 0x0000 - 0x7fff
- Bit pattern: 0b0...............
-
- RAM access must happen only in secon half of cycle, therefore
- oe#, ce#, and we# are qualified by !phi.
- */
-
-o1 = !phi # !rwb; /* ram_#oe */
-o3 = !phi # i0; /* ram_#ce */
-o6 = !phi # rwb; /* ram_#we */
-
-/* In order to drive up to 4 I/O devices from 3 output lines, we
- exploit that both the 6522 and the 6551 have two ce lines, of which
- one must be logic 1 and the other logic 0. In the table below,
- columns ce and #ce indicate which lines should be connected to ce
- and #ce of the I/O device given in the row. The third column ensure
- that all selections are distinct. Column four and five assign
- the I/O devices to input addresses.
-
- ce #ce i3 i4
- acia1 : o2 & !o4 & !o5 0 0
- via1 : o4 & !o2 & o5 0 1
- acia2 : o5 & !o4 & !o2 1 0
- via2 : o4 & !o5 & o2 1 1
-
- We place the I/O devices right below the ROM,
- i.e. i0 i1 i2 == 0b110, resulting in the
- following address mapping:
-
- acia1 : 0b11000........... = 0xc000 .. 0xc7ff
- via1 : 0b11001........... = 0xc800 .. 0xcfff
- acia2 : 0b11010........... = 0xd000 .. 0xd7ff
- via2 : 0b11011........... = 0xd800 .. 0xdfff
-
-*/
-
-o2 = ((!i3 & !i4) # (i3 & i4)) & i0 & i1 & !i2;
-o4 = ((!i3 & i4) # (i3 & i4)) & i0 & i1 & !i2;
-o5 = ((!i3 & i4) # (i3 & !i4)) & i0 & i1 & !i2;
-
-/* Inverter
- This is not part of the bus logic.
- The reset logic needs an inverter.
- We provide it here.
-*/
-
-o7 = !reset_in;
diff --git a/hw/bus_logic/Makefile b/hw/bus_logic/Makefile
@@ -0,0 +1,12 @@
+TARGET=bus_logic
+
+all: ${TARGET}.jed
+
+${TARGET}.jed: ${TARGET}.pld
+ ~/opt/GALasm/src/galasm $<
+
+clean:
+ rm -f ${TARGET}.chp ${TARGET}.fus ${TARGET}.pin ${TARGET}.jed
+
+flash: ${TARGET}.jed
+ sudo ~/opt/minipro-0.5/minipro -p ATF16V8B -w $<
diff --git a/hw/bus_logic/bus_logic.pld b/hw/bus_logic/bus_logic.pld
@@ -0,0 +1,66 @@
+GAL16V8 ; Actually an ATF16V8
+Eris2010 ; Eris 2010 Bus Logic
+
+rwb a15 a14 a13 a12 a11 a10 resetin phi GND
+NC romceb ramoeb iosel2 ramceb iosel4 iosel5 ramweb resb VCC
+
+
+romceb = /a15 + /a14 + /a13
+
+ramoeb = !phi + !rwb
+ramceb = !phi + a15
+ramweb = !phi + rwb
+
+iosel2 = !a12 * !a11 * a15 * a14 * !a13
+ + a12 * a11 * a15 * a14 * !a13
+iosel4 = !a12 * a11 * a15 * a14 * !a13
+ + a12 * a11 * a15 * a14 * !a13
+iosel5 = !a12 * a11 * a15 * a14 * !a13
+ + a12 * !a11 * a15 * a14 * !a13
+
+resb = !resetin
+
+DESCRIPTION
+
+Eris 2010 Bus Logic
+
+Pin names should be mostly self-explanatory, e.g. ramoeb is OE of the
+RAM. The "b" indicates that this line is active on low.
+
+resetin is the reset signal coming from reset line. This line is high
+on reset. Since resb is active low, it gets inverted.
+
+ROM and RAM are mapped as follows:
+
+ rom : 0b111............. = 0xe000 .. 0xffff
+ ram : 0b0............... = 0x0000 .. 0x7fff
+
+ RAM must be accessed in the in second half of a clock cycle only,
+ therefore ramoeb, ramceb, and ramweb are qualified by !phi.
+
+iosele2, iosel4, and iosel5 select beteen 4 peripheral devices. An
+ACIA (providing the main serial interface), and a VIA (communication
+interface to SD card and GPIO pins) are part of Eris 2010. Two more
+devices can be added via the Expansion Port. These four devices are
+activated as follows:
+
+ Output Input
+
+ ce #ce a15 a14 a13 a12 a11
+ acia1 : o2 & !o4 & !o5 1 1 0 0 0
+ via1 : o4 & !o2 & o5 1 1 0 0 1
+ exp1 : o5 & !o4 & !o2 1 1 0 1 0
+ exp2 : o4 & !o5 & o2 1 1 0 1 1
+
+This defines the following memory mapping for the periperhal devices:
+
+ acia1 : 0b11000........... = 0xc000 .. 0xc7ff
+ via1 : 0b11001........... = 0xc800 .. 0xcfff
+ exp1 : 0b11010........... = 0xd000 .. 0xd7ff
+ exp2 : 0b11011........... = 0xd800 .. 0xdfff
+
+
+
+Copyright 2021 Gerd Beuster (gerd@frombelow.net). This is free
+soft-/hardware under the GNU GPL v3 license or any later version. See
+COPYING in the root directory for details.
