eris2010

Documentation: http://frombelow.net/projects/eris2010/
Clone: git clone https://git.frombelow.net/eris2010.git
Log | Files | Refs | README | LICENSE

bus_logic.pld (2181B)


      1 GAL16V8  ; Actually an ATF16V8
      2 Eris2010 ; Eris 2010 Bus Logic
      3 
      4 rwb    a15    a14    a13    a12    a11    a10 resetin  phi GND
      5 NC  romceb ramoeb iosel2 ramceb iosel4 iosel5  ramweb resb VCC
      6 
      7 
      8 romceb =   /a15 + /a14 + /a13
      9 
     10 ramoeb = !phi + !rwb
     11 ramceb = !phi + a15
     12 ramweb = !phi + rwb
     13 
     14 iosel2 =   !a12 * !a11 * a15 * a14 * !a13
     15          +  a12 *  a11 * a15 * a14 * !a13
     16 iosel4 =   !a12 *  a11 * a15 * a14 * !a13
     17          +  a12 *  a11 * a15 * a14 * !a13
     18 iosel5 =   !a12 *  a11 * a15 * a14 * !a13
     19          +  a12 * !a11 * a15 * a14 * !a13
     20 
     21 resb = !resetin
     22 
     23 DESCRIPTION
     24 
     25 Eris 2010 Bus Logic
     26 
     27 Pin names should be mostly self-explanatory, e.g. ramoeb is OE of the
     28 RAM. The "b" indicates that this line is active on low.
     29 
     30 resetin is the reset signal coming from reset line. This line is high
     31 on reset. Since resb is active low, it gets inverted.
     32 
     33 ROM and RAM are mapped as follows:
     34 
     35    rom : 0b111............. = 0xe000 .. 0xffff
     36    ram : 0b0............... = 0x0000 .. 0x7fff
     37 
     38    RAM must be accessed in the in second half of a clock cycle only,
     39    therefore ramoeb, ramceb, and ramweb are qualified by !phi.
     40 
     41 iosele2, iosel4, and iosel5 select beteen 4 peripheral devices. An
     42 ACIA (providing the main serial interface), and a VIA (communication
     43 interface to SD card and GPIO pins) are part of Eris 2010. Two more
     44 devices can be added via the Expansion Port. These four devices are
     45 activated as follows:
     46 
     47            Output                Input
     48 
     49 	   ce   #ce              a15 a14 a13       a12 a11       
     50    acia1 : o2 & !o4   & !o5        1   1   0         0   0
     51    via1  : o4 & !o2   &  o5        1   1   0         0   1
     52    exp1  : o5 & !o4   & !o2        1   1   0         1   0
     53    exp2  : o4 & !o5   &  o2        1   1   0         1   1
     54 
     55 This defines the following memory mapping for the periperhal devices:
     56 
     57    acia1 : 0b11000........... = 0xc000 .. 0xc7ff
     58    via1  : 0b11001........... = 0xc800 .. 0xcfff
     59    exp1  : 0b11010........... = 0xd000 .. 0xd7ff
     60    exp2  : 0b11011........... = 0xd800 .. 0xdfff
     61 
     62 
     63 
     64 Copyright 2021 Gerd Beuster (gerd@frombelow.net). This is free
     65 soft-/hardware under the GNU GPL v3 license or any later version. See
     66 COPYING in the root directory for details.