eris2206

uart.v (5145B)

---

 /*
  * Copyright 2022 Gerd Beuster (gerd@frombelow.net). This is free
  * soft-/hardware under the GNU GPL v3 license or any later
  * version. See COPYING in the root directory for details.
  */
 
 `ifndef uart_v
  `define uart_v
 
 // In order to send a byte, din is set to the byte to be send and
 // write is set to 1. While transmitting, bit 0 of the status register
 // is 1.
 //
 // In order to receive a byte, the receive buffer must be cleared by
 // writing to the status register. Once the byte is received, bit 1 of
 // the status register is set to 1.
 
 module uart(input clk, // 12 Mhz system clock
             // Data to be send via the serial line is read from din.
             input [7:0]  din,
 	    // When reg_select is set to 0 (see below), dout carries
 	    // the last byte received via the serial line.
 	    // When reg_select is set to 1, dout carries the current bits:
 	    // Bit 0: The UART is in the process of sending the byte at din
 	    // Bit 1: The UART received a byte.
             output [7:0] dout,
 	    // When reg_select is set to 0 (see below), setting write to 1
 	    // starts serial transmission of din.
 	    // When reg_select is set to 1, setting write to 1 clears
 	    // the receive buffer.
             input 	 write,
 	    //  0: Data Register
 	    //  1: Status register
             input 	 reg_select,
             // Connections to hardware lines
             output reg 	 tx,
             input 	 rx);
 
    reg [9:0]             tx_buffer; // Internal transmit buffer (start bit, data, stop bit)
    reg [7:0]             rx_buffer; // Internal receive buffer
    reg [7:0]             received_byte; // Last complete byte received
    reg [7:0]             bit_time_tx; // Clock ticks until bit transmitted
    reg [3:0]             curr_bit_tx; // Index of bit currently transmitted
    reg                   rx_busy;
    reg                   tx_busy;
    wire                  recv_buffer_full;
 
    parameter ticks_per_bit = 104; // Clock ticks per bit for 115200 bps @ 12 Mhz
 
    assign dout = reg_select ? {6'b000000, recv_buffer_full, tx_busy} : received_byte;
 
    initial
      begin
         tx_busy <= 0;
         tx <= 1;
         curr_bit_tx <= 0;
         rx_busy <= 0;
      end
 
    /*
     * Transmitter
     *
     */
 
    always @(posedge(clk))
      begin
         // Begin of transmission
         if (write && !reg_select && !tx_busy)
           // Transmissions starts on write operation to data register:
           // Fill the internal transmit buffer, and get busy.
           begin
              tx_buffer <= {1'b1, din, 1'b0};
              curr_bit_tx <= 0;
              bit_time_tx <= ticks_per_bit;
              tx_busy <= 1;
           end
         // End of transmission
         if (curr_bit_tx == 10)
           begin
              // Keep tx high will not transmitting.
              tx <= 1;
              // If the CPU clock is significangtly slower than the
              // system clock, write may still be high. In order to
              // avoid sending the same byte again, we only set tx_busy
              // to low when write is low as well.
              if(!write)
                begin
                   tx_busy <= 0;
                   curr_bit_tx <= 0;
                end
           end // if (curr_bit_tx == 10)
         else
           // In transmission
           begin
              if (tx_busy)
                // Output current bit
                begin
                   tx <= tx_buffer[curr_bit_tx];
                   bit_time_tx <= bit_time_tx - 1;
                end
              if (bit_time_tx == 0)
                // Switch to next bit
                begin
                   curr_bit_tx <= curr_bit_tx + 1;
                   bit_time_tx <= ticks_per_bit;
                end
           end
      end // always @ (posedge(clk))
 
    /*
     * Receiver
     *
     */
 
    reg [7:0] bit_time_rx; // Clock ticks until bit received
    reg [3:0] curr_bit_rx; // Index of bit currently received
 
    assign recv_buffer_full = (curr_bit_rx == 9);
    always @(posedge(clk))
      begin
         if (write && reg_select)
           curr_bit_rx <= 0;
         else
           begin
              if (!rx_busy && !rx)
                begin
                   // Start receving once we get the start bit
                   rx_busy <= 1;
                   curr_bit_rx <= 0;
                   // bit_time_rx hits 0 in the middle
                   // of the first data bit
                   bit_time_rx <= ticks_per_bit * 1.5;
                end
              else if ((curr_bit_rx == 9) && rx)
                begin
                   // If this is the stop bit, we are done
                   rx_busy <= 0;
                   received_byte <= rx_buffer;
                end
              else if ((rx_busy) && (bit_time_rx == 0))
                // We are in the middle of the next bit.
                begin
                   // Read it
                   rx_buffer[curr_bit_rx] <= rx;
                   curr_bit_rx <= curr_bit_rx + 1;
                   bit_time_rx <= ticks_per_bit;
                end
              else
                bit_time_rx <= bit_time_rx - 1;
           end
      end // always @ (posedge(clk))
 
 endmodule
 
 `endif