eris2206

ecpu.v (21066B)

---

 /*
  * Copyright 2022 Gerd Beuster (gerd@frombelow.net). This is free
  * soft-/hardware under the GNU GPL v3 license or any later
  * version. See COPYING in the root directory for details.
  */
 
 `ifndef ecpu_v
  `define ecpu_v
 
  `include "uart.v"
  `include "ws2811.v"
 
 module esoc( // System operates at this clock speed in run mode
              input       slow_clk,
             // Resets counters and registers, RAM is not deleted!
              input       reset_in,
             // Switch between memory set mode andexecution mode
              input       program_mode,
             // Single step mode or continous execution
              input       single_cont,
              // Step trigger in single step mode, write data in
              // set memory mode.
              input       step,
              // Skip memory cell in set memory mode
              input       skip,
              input [7:0] din, // Data bus input in set memory mode
              // GPIO (LEDs)
              output      green, output red_n, output red_e, output red_s,
              output      red_w,
             // Fast clock for timing sensitive modules (UART & WS2811)
              input       fast_clk,
             // UART
              output      tx, input rx,
             // WS2811
              output      ws2811_dout);
 
    // The default ROM contains two programs:
    //
    // - Computation of Fibonacci numbers (at $80)
    //
    // This program is located at the start of the ROM, and thus gets
    // executed on power on
    //
    // - Second stage bootloader (at $C0)
    //
    // The bootloader loads a program via the serial line. (See
    // tools/send_serial.py for the upload program.) In order to use it,
    // the user has to ener a minimal first stage bootloader, which
    // jumps into this second stage bootloader, via the front panel
    // switches.
    parameter rom_file = "roms/rom.dat";
 
    // This ROM shows a sequence on the built-in LEDs of the
    // iCEstick. Since the iCEstick is embedded in the case, the LEDs
    // are only visible when the cas is opened.
    // parameter rom_file = "roms/rom_leds.dat";
 
    // A serial echo program to test the UART.
    // parameter rom_file = "roms/rom_uart.dat";
 
    // The program to test all opcodes had to be split in two parts. As
    // the result of each opcode test, the value $FF should be written
    // to memory.
    // parameter rom_file = "roms/rom_opcode_test_0.dat";
    // parameter rom_file = "roms/rom_opcode_test_1.dat";
 
    //
    // Operation modes
    //
 
    // There are two main modes:
    //
    // - In execution mode, the CPU runs all components
    //
    // - In memory set mode, modul manual_programmer controls the
    // address bus and the memory write line. Data input comes straight
    // from the switches set by the user.
    wire [7:0]           data_bus, address_bus, cpu_address_bus, programmer_address_bus;
    wire                 mem_set, cpu_mem_set, programmer_mem_set;
    wire                 cpu_clk;
    // In programming mode, the CPU clock is stopped. In exeuction mode, it
    // normally runs on the slow clock, unless we are in singel step mode.
    assign cpu_clk = program_mode ? 0 :
                     ((single_cont | reset_in) ? slow_clk : step);
    assign mem_set = program_mode ? programmer_mem_set : cpu_mem_set;
    assign data_bus = program_mode ? din : cpu_dout;
    assign address_bus = program_mode ? programmer_address_bus : cpu_address_bus;
 
    manual_programmer mp(.clk(fast_clk), .res(reset_in),
                         .step(step), .skip(skip),
                         .mem_set(programmer_mem_set),
                         .aout(programmer_address_bus));
 
    //
    // Glue logic: Memory mapping of peripherals
    //
 
    // The CPU addresses a flat memory space. Here we define glue logic
    // to map this flat memory space to access to RAM, ROM, UART, and
    // GPIO.
    //
    // The lower 5 bits of $FD turn the LEDs of the iCEstick on and off.
 
    // hFF     : UART - Write: Clear recv_buffer_full
    //               - Read: Status (0: TX busy, 1: recv_buffer_full)
    // hFE     : UART - Write: Send Data - Read: Received Data
    // $FD     : I/O (0..5: LEDs)
    // h80-hFC : ROM
    // h00-h7F : RAM
 
    // Data input for the CPU may come from ROM, RAM, or UART.
    wire [7:0]           mem_dout; // CPU data (memory) input
    // Data output of ROM, RAM, and UART
    wire [7:0]           rom_dout, ram_dout, uart_dout;
    // Map data output to CPU data input according to memory map
    assign mem_dout = (address_bus < 8'h80) ? ram_dout :
                      ((address_bus < 8'hFE) ? rom_dout : uart_dout);
    wire [7:0]           cpu_dout;
    // Set correct device to write mode
    wire                 ram_set, gpio_set, uart_set;
    assign ram_set = (address_bus < 8'h80) ? mem_set : 0;
    assign gpio_set = (address_bus == 8'hFD) ? mem_set : 0;
    assign uart_set = (address_bus > 8'hFD) ? mem_set : 0;
 
    //
    // CPU and peripherals definitions
    //
 
    wire [15:0]          control_logic;
    wire [7:0]           reg_a_value;
    wire [7:0]           alu_value;
    wire [7:0]           pc_value;
    wire [7:0]           dp_value;
    ecpu e(.clk(cpu_clk),
           .reset_in(reset_in),
           .mem_dout(mem_dout),
           .mem_set(cpu_mem_set),
           .data_bus(cpu_dout),
           .address_bus(cpu_address_bus),
           .ctrl_logic_mon(control_logic),
           .reg_a_value(reg_a_value),
           .alu_value(alu_value),
           .pc_value(pc_value),
           .dp_value(dp_value));
 
    ram ram_mem(.clk(fast_clk), .set(ram_set),
                .din(data_bus), .dout(ram_dout), .ain(address_bus[6:0]));
 
    rom
      #(.rom_file(rom_file))
    rom_mem(.clk(fast_clk), .dout(rom_dout), .ain(address_bus[6:0]));
 
 
    gpio g(.clk(fast_clk), .din(data_bus[4:0]), .write(gpio_set),
 	      .green(green),  .red_n(red_n), .red_e(red_e),
 	      .red_s(red_s), .red_w(red_w));
 
    // UART reg_select is connected to the LSB of the address bus, thus
    // mapping the two UART registers to two consequtive memory addresses.
    // The start wire connects to the write signal of the CPU: Writing
    // data two the UART starts transmission.
    // The UART must be driven by a 12 Mhz clock.
    uart u(.clk(fast_clk), .din(data_bus), .dout(uart_dout),
           .reg_select(address_bus[0]), .write(uart_set), .tx(tx), .rx(rx));
 
    // Monitor: Show internal state of system on LED matrix
  `define VRAM_SIZE 32
    led_monitor #(.vram_size(`VRAM_SIZE))
    led_mon (.fast_clk(fast_clk),
             .data_bus(data_bus),
             .address_bus(address_bus),
             .mem_set(mem_set),
             .control_logic(control_logic),
             .reg_a(reg_a_value),
             .alu(alu_value),
             // We set value to address bus in program mode in order
             // to highlight the address currently manipulated
             .pc(program_mode ? address_bus : pc_value),
             .dp(dp_value),
             .ws2811_dout(ws2811_dout));
 
 endmodule // esoc
 
 module ecpu(input clk,
             input         reset_in,
             input [7:0]   mem_dout,
             output        mem_set,
             output [7:0]  data_bus,
             output [7:0]  address_bus,
             output [15:0] ctrl_logic_mon, // Monitor output
             output [7:0]  reg_a_value,
             output [7:0]  alu_value,
             output [7:0]  pc_value,
             output [7:0]  dp_value);
 
    // While the control logic of the CPU operates on negative clock
    // edges, the components operate on positive edges.
 
    // Enable/disable lines for components
    // PC
    wire                   pc_set, pc_inc;
    // The comperator connects microcode for conditional
    // (pc_set_if_zero, pc_set_if_nonzero) and unconditional
    // (pc_set_uncond) jumps to the set signal of the PC (pc_set).
    wire                   pc_set_if_zero, pc_set_if_nonzero, pc_set_uncond;
    // MIP
    wire                   mip_set;
    // DP
    wire                   dp_set, dp_get;
    // Accumulator
    wire                   reg_a_get, reg_a_zero;
    // Accumulator does not only allow setting, but more
    // commands (inc, dec, ...).
    wire [2:0]             reg_a_cmd;
    // ALU
    // Three bits determine which result we get from the ALU:
  `define alu_off 3'b000
  `define alu_add 3'b001
  `define alu_sub 3'b010
    // Multiplication and division occpuy too many PLBs
 /* -----\/----- EXCLUDED -----\/-----
  `define alu_mul 3'b011
  `define alu_div 3'b100
  -----/\----- EXCLUDED -----/\----- */
  `define alu_and 3'b101
  `define alu_or  3'b110
  `define alu_xor 3'b111
    wire [2:0]             alu_get;
 
    // Glue logic: Since all components may write to the buses, write
    // access to the buses must be multiplexed.
    wire [7:0]             pc_dout, dp_dout, mip_dout, reg_a_dout, alu_dout;
    // Multiplexer for address bus:
    // If dp_get is set, the data pointer is loaded on the address bus.
    // Otherwise the program counter is loaded on the address bus.
    assign address_bus = dp_get ? dp_dout : pc_dout;
    // Multiplexer for data bus
    // Unless the data bus is explicitly loaded with the accumulator
    // or the ALU, it is loaded from memory.
    wire [7:0]             alu_sum;
    wire [7:0]             alu_difference;
    wire [7:0]             alu_and;
    wire [7:0]             alu_or;
    wire [7:0]             alu_xor;
    assign alu_value = (alu_get == `alu_add) ? alu_sum :
                       ((alu_get == `alu_sub) ? alu_difference :
                        ((alu_get == `alu_and) ? alu_and :
                         ((alu_get == `alu_or) ? alu_or :
                          ((alu_get == `alu_xor) ? alu_xor :
                           alu_sum))));
    assign data_bus = reg_a_get ? reg_a_dout :
                      ((alu_get == `alu_off) ? mem_dout : alu_value);
    // Monitor output
    assign ctrl_logic_mon = { clk, pc_set_uncond, pc_set_if_zero,
                              pc_set_if_nonzero,
                              pc_inc, dp_set, dp_get,
                              mip_set, reg_a_cmd, reg_a_get,
                              mem_set, alu_get } ;
    assign reg_a_value = reg_a_dout;
    assign pc_value = pc_dout;
    assign dp_value = dp_dout;
 
    // Reset logic
    reg                    res = 1;
    always @(posedge(clk))
      res <= reset_in;
 
 
    control_logic ctrl (.clk(clk),
                        .res(res),
                        .pc_set_uncond(pc_set_uncond),
                        .pc_set_if_zero(pc_set_if_zero),
                        .pc_set_if_nonzero(pc_set_if_nonzero),
                        .pc_inc(pc_inc),
                        .dp_set(dp_set), .dp_get(dp_get),
                        .mip_set(mip_set),
                        .mip_value(mip_dout),
                        .reg_a_cmd(reg_a_cmd), .reg_a_get(reg_a_get),
                        .mem_set(mem_set),
                        .alu_get(alu_get));
 
 
    // Program Counter
    counter
      #(.start_value(8'h80)) // Start execution in ROM
    pc (.clk(clk), .res(res),
        .set(pc_set), .inc(pc_inc),
        .din(data_bus), .dout(pc_dout));
 
    // The micro instruction pointer (mip) keeps track of the current
    // micro instruction. It is updated from the data bus (when the
    // next opcode is read, because opcode = pointer to begin of
    // microcode implementation of opcode) and read by the control
    // logic.
    //
    // The increment input is fixed to high, because the MIP shall
    // always step to the next instruction always, unless a new
    // value is set.
    counter mip (.clk(clk), .res(res),
                 .set(mip_set), .inc(1'b1),
                 .din(data_bus), .dout(mip_dout));
 
    // The data pointer reads from data bus and writes to the address
    // bus. It is used to dereference memory addresses.
    register dp (.clk(clk), .res(res),
                 .set(dp_set), .inc(1'b0), .dec(1'b0),
                 .rol(1'b0), .ror(1'b0), .inv(1'b0),
                 .din(data_bus), .dout(dp_dout));
 
    // Accumulator
    // The accumulator supports additional operations besides setting.
    // We demultiplex the reg_a_cmd for this
    wire                   reg_a_set, reg_a_inc, reg_a_dec, reg_a_rol,
                           reg_a_ror, reg_a_inv;
    assign reg_a_set = (reg_a_cmd == 3'b001);
    assign reg_a_inc = (reg_a_cmd == 3'b010);
    assign reg_a_dec = (reg_a_cmd == 3'b011);
    assign reg_a_rol = (reg_a_cmd == 3'b100);
    assign reg_a_ror = (reg_a_cmd == 3'b101);
    assign reg_a_inv = (reg_a_cmd == 3'b110);
    register reg_a (.clk(clk), .res(res),
                    .set(reg_a_set), .inc(reg_a_inc), .dec(reg_a_dec),
                    .rol(reg_a_rol), .ror(reg_a_ror), .inv(reg_a_inv),
                    .din(data_bus), .dout(reg_a_dout), .zero(reg_a_zero));
 
    // Comperator
    // The program counter is set from the data bus (i.e. a jump is
    // executed) when we execute the microcode for an unconditional
    // jump (pc_set_uncond) or when we execute the microcode for a
    // conditional jump (pc_set_if_zero) and the zero flag of the
    // accumulator is set.
    assign pc_set = pc_set_uncond | (pc_set_if_zero & reg_a_zero) |
                    (pc_set_if_nonzero & !reg_a_zero);
 
    // ALU
    // The ALU consists of an adder and a register. The adders gets the
    // accumulator and the data bus as input and updates the register.
    // The register writes to the data bus.
    alu a(.clk(clk), .din_a(reg_a_dout), .din_b(data_bus), .sum(alu_sum),
          .difference(alu_difference), .band(alu_and), .bor(alu_or),
          .bxor(alu_xor));
 endmodule
 
 module counter(input        clk,
                input        res,
                input        set,
                input        inc,
                input [7:0]  din,
                output [7:0] dout);
 
    // Start value is only set on initialization. Reset
    // always sets counter to 0, not back to start value.
    // By setting the start value of the PC to the first
    // ROM address, the SOC will run from ROM on power-up,
    // but can be programmed starting from address h00
    // on reset.
    parameter start_value = 8'h00;
    reg [7:0]                value;
    reg                      init = 0;
 
    assign dout = value;
    always @(posedge(clk))
      if (init == 0)
        begin
           value <= start_value;
           init <= 1;
        end
      else
        if (res)
          value <= 8'h00;
        else if (set)
          value <= din;
        else if (inc)
          // Only increment value if no new value is set. This order is
          // important for two reasons:
          // - Conditional jumps always increment the PC.
          //   This should only have an effect if no new address is set.
          // - For the MIP, inc is fixed to high. If mip_set sets a new
          //   new address, the new address should not increment immediately.
          value <= value + 1;
 endmodule
 
 module alu(input clk, input [7:0]  din_a, input [7:0]  din_b,
            output reg [7:0] sum,
            output reg [7:0] difference,
            output reg [7:0] band,
            output reg [7:0] bor,
            output reg [7:0] bxor);
    always @(posedge(clk))
      begin
         sum <= din_a + din_b;
         difference <= din_a - din_b;
    // Multiplication and division occpuy too many PLBs
 /* -----\/----- EXCLUDED -----\/-----
         product <= din_a * din_b;
         quotient <= din_a / din_b;
  -----/\----- EXCLUDED -----/\----- */
         band <= din_a & din_b;
         bor <= din_a | din_b;
         bxor <= din_a ^ din_b;
      end
 endmodule
 
 module register(input        clk,
                 input        res,
                 input        set,
                 input        inc,
                 input        dec,
                 input        rol,
                 input        ror,
                 input        inv,
                 input [7:0]  din,
                 output [7:0] dout,
                 output       zero);
 
    reg [7:0]                 value;
 
    assign dout = value;
    assign zero = (value == 0);
    always @(posedge(clk))
      if (res)
        value <= 8'b00000000;
      else if (set)
        value <= din;
      else if (inc)
        value <= value + 1;
       else if (dec)
        value <= value - 1;
      else if (rol)
        value <= { value[6], value[5], value[4], value[3],
                   value[2], value[1], value[0], value[7] };
      else if (ror)
        value <= { value[0], value[7], value[6], value[5],
                   value[4], value[3], value[2], value[1] };
      else if (inv)
        value <= value ^ 8'b11111111;
 endmodule
 
 // 128 byte RAM module
 module ram(input            clk,
            input            set, // Write din to memory cell
            input [7:0]      din,
            output reg [7:0] dout,
            input [6:0]      ain);
 
    reg [7:0]                mem [0:127];
    always @(posedge(clk))
      begin
         if (set)
           mem[ain] <= din;
         dout <= mem[ain];
      end
 endmodule
 
 // 128 byte ROM module
 module rom(input            clk,
            output reg [7:0] dout,
            input [6:0]      ain);
 
    parameter rom_file = "roms/rom.dat";
 
    reg [7:0]            mem [0:127];
 
    always @(posedge(clk))
      begin
         dout <= mem[ain];
      end
 
    initial
 	 $readmemh(rom_file, mem);
 endmodule
 
 module gpio(input clk, input [4:0]      din,
             input      write,
             output reg green, output reg red_n, output reg red_e,
             output reg red_s, output reg red_w);
 
    always @(posedge(clk))
      if (write)
        { red_n, red_e, red_s, red_w, green} <= din;
 endmodule
 
 //  All microcode is stored in array microcode_(lsb|msb). The data for
 //  this arrays is generated by tools/mc_compiler.py. Pointers to the
 //  microcode for an opcode are stored in array ptr_opcode_microcode.
 //  These arrays are initialized upon reset.
 module control_logic(input clk, input res,
                      output reg       pc_set_uncond,
                      output reg       pc_set_if_zero,
                      output reg       pc_set_if_nonzero,
                      output reg       pc_inc,
                      output reg       dp_set, dp_get,
                      output reg       mip_set,
                      input [7:0]      mip_value,
                      output reg       mem_set,
                      output reg       reg_a_get,
 		             output reg [2:0] reg_a_cmd,
                      output reg [2:0] alu_get);
 
    // Used to set all enable/disable signals in one go
  `define execute_microcode {alu_get, \
                             mip_set, \
                             reg_a_cmd, reg_a_get, \
                             mem_set, \
                             dp_get, dp_set, \
                             pc_inc, \
                             pc_set_if_nonzero, pc_set_if_zero, pc_set_uncond}
 
    reg [7:0]                     microcode_lsb [0:145];
    reg [6:0]                     microcode_msb [0:145];
 
    // Microcode for the assembler opcodes is defined in
    // tools/mc_compiler.py. During synthesis,
    // mc_compiler.py writes the microcode for the assembler
    // opcodes into a ROM file, which is read here.
    initial
      begin
         $readmemh("tools/microcode_rom_lsb.dat", microcode_lsb);
         $readmemh("tools/microcode_rom_msb.dat", microcode_msb);
      end
 
    always @(negedge(clk))
      if (res)
        `execute_microcode <= 0;
      else
        `execute_microcode <= { microcode_msb[mip_value],
                                microcode_lsb[mip_value] };
 
 endmodule
 
 module manual_programmer(input clk, input res,
                          input            step,
                          input            skip,
                          output reg       mem_set,
                          output reg [7:0] aout);
    reg                                    state;
    // The monitor (LED matrix) does not access the system memory.
    // Instead it listens to the address and data busses and maintainces
    // its own memory. Since the monitor update operation either updates
    // the registers or the memory, it may miss a memory updates if we
    // update the memory too fast here. In order to fix this problem, the
    // write signal is kept up for time given by write_delay.
    reg [3:0]                              write_delay;
  `define state_set_data 0
  `define state_write_or_skip_data 1
    initial
      begin
         state <= `state_set_data;
         aout <= 8'h00;
         mem_set <= 0;
      end
    always @(posedge(clk))
      if (res)
        begin
           state <= `state_set_data;
           aout <= 8'h00;
           mem_set <= 0;
        end
      else
        case (state)
          `state_set_data:
            if (step || skip)
              begin
                 state <= `state_write_or_skip_data;
                 mem_set <= !skip;
                 write_delay <= -1;
              end
          `state_write_or_skip_data:
            begin
               if (write_delay == 0)
                 begin
                    mem_set <= 0;
                    state <= `state_set_data;
                    aout <= aout + 1;
                 end
               write_delay <= write_delay - 1;
            end
        endcase
 endmodule
 
 `endif