Makefile (1145B)
1 TARGET=ecpu 2 INC=-I../inc 3 ROMS=roms/rom.dat roms/rom_opcode_test_0.dat roms/rom_opcode_test_1.dat \ 4 roms/rom_leds.dat roms/rom_uart.dat 5 6 all: binary simulation 7 8 binary: $(TARGET).bin 9 10 %.s: %.asm 11 cpp -nostdinc -C -P -o $@ $< 12 13 # Assemble programs for SOC 14 %.dat: %.s tools/opcodes.pl 15 tools/eras.pl $< $@ 16 17 tools/opcodes.pl: 18 cd tools; python3 ./mc_compiler.py opcodes 19 20 %.s: %.asm 21 cpp -nostdinc -C -P -o $@ $< 22 23 # Synthesize 24 %.blif: %.v main.v uart.v $(ROMS) 25 cd tools; python3 ./mc_compiler.py microcode 26 yosys -p "read_verilog $(INC) main.v; synth_ice40 -blif $@" 27 28 # Place and route 29 %.txt: %.blif 30 arachne-pnr -d 1k -p $(TARGET).pcf $< -o $@ 31 32 # Convert to bitstream 33 %.bin: %.txt 34 icepack $< $@ 35 36 # Upload 37 upload: $(TARGET).bin 38 iceprog ${ICEPROG_ARGS} $< 39 40 # Simulation 41 simulation: $(TARGET).v $(ROMS) 42 cd tools; python3 ./mc_compiler.py microcode 43 iverilog $(INC) -o $(TARGET).out $(TARGET)_tb.v 44 ./$(TARGET).out 45 gtkwave $(TARGET)_tb.vcd $(TARGET)_tb.gtkw 46 47 clean: 48 rm -f *.txt *.bin *.blif *.out *.vcd roms/*.s $(ROMS) tools/opcodes.pl \ 49 tools/microcode_rom_lsb.dat tools/microcode_rom_msb.dat 50 51 .PHONY: all clean upload simulation binary